 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| DATA SHEET MOS INTEGRATED CIRCUIT PD98411 ATM QUAD SONET FRAMER The PD98411 NEASCOT-P40 is one of ATM-LAN LSIs and provides the functions of the TC sublayer of the SONET/SDH-base physical layer of the ATM protocol specified by the ATM Forum. Its main functions include a transmission function to map an ATM cell passed from an ATM layer to the payload of 155M-bps SONET STS3c/SDH STM-1 frame and transmit the cell to the PMD (Physical Media Dependent) sublayer of the physical layer, and a reception function to separate the overhead and ATM cell from the data string received from the PMD device and transmit the ATM cell to the ATM layer. The PD98411 NEASCOT-P40 combines these transmission This LSI is ideally suited for /reception functions into a port function that is realized as a single 4-port LSI chip. use in the ATM hubs, ATM switches, and other equipment used to configure an ATM network. In addition, the PD98411 also has a clock recovery function for each port to extract synchronous clock for reception of receive data from the bit stream, and a clock synthesis function to generate a clock for transmission. For the details of functional description, refer to the following user's manual. PD98411 User's Manual : S12736E FEATURES * * * * Incorporates an ATM user network interface TC sublayer function for four channels. Conforms to ATM FORUM UNI v3.1. Incorporates four clock recovery PLLs and one clock synthesizer PLL. Conforms to ATM FORUM UTOPIA Level 2 v1.0. * ATM layers can be selected from the multi-PHY interface (up to 800 Mbps) in several different modes. Single 16-bit Single 8-bit Dual 8-bit 1TCLAV/1RCLAV (Cell Available signal mode) Direct Status Indication mode Multiplexed Status Polling mode * A management interface can be set to either of two modes. RD-WR-RDY style (Intel-compatible mode) DS-R/W-ACK style (Motorola-compatible mode) * * * * * The line-side PMD interface accepts a P-ECL level input. Supports a loopback function. Supports a pseudo error generation frame transmission function. Incorporates one general input port per channel and three output ports (each able to drive an LED) per channel. Supports JTAG boundary scan test (IEEE 1149.1). The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S12953EJ4V0DS00 (4th edition) Date Published January 1999 NS CP(K) Printed in Japan (c)NEC Corporation 1997,1999 PD98411 * Incorporates a wide range of operation, administration, and maintenance (OAM) functions. Transmission Alarm Condition and Failure Detection APS Line AIS/Path AIS Line RDI/Path RDI Line Quality Monitoring Insertion of B1-byte computation Insertion of B2-byte computation Insertion of B3-byte computation Automatic transmission of a Line REI Automatic transmission of a Path REI Reception Alarm Condition and Failure Detection External input signal change LOS OOF LOF LOP OCD LCD Line AIS/Path AIS Line RDI/Path RDI APS Notification of Degraded Line Quality B1 error B2 error B3 error Line REI Path REI Frequency justification FIFO overflow Line Quality Monitor Counter B1 error counter B2 error counter B3 error counter Line REI counter Path REI counter Frequency justification counter HEC processing dropped cell counter FIFO overflow dropped cell counter Received idle cell counter Valid cell counter * * 0.35-m CMOS process Low power consumption; +3.3 V single-voltage power supply ORDERING INFORMATION Part Number Package 240-pin plastic QFP (fine pitch) (32 x 32 mm) PD98411GN-MMU 2 Data Sheet S12953EJ4V0DS00 PD98411 APPLICATIONS The following are examples of the application using the PD98411. * ATM Switches NIC PD98411 155 ATM Interface OC-12 SONET Framer PD98411 NIC SWITCH Backbone Network PD98411 NIC PD98411 UTOPIA Level2 CPU Data Sheet S12953EJ4V0DS00 3 PD98411 SYSTEM CONFIGURATION 1) PD98411 System Application PMD I/F (PECL) Status OSC (19.44M) Optical Module Multimode Fiber PD98411 ATM Layer Device Tx UTOPIA I/F Optical Module (NEASCOT-P40) Equalizer Components Magnetics RJ-45 Connector Shielded Twist Pair Rx UTOPIA I/F Management I/F Equalizer Components Magnetics RJ-45 Connector Processor 2) Connection to 5-V transceiver/receiver The following show an example of connecting the PD98411 to a 5-V optical transceiver. Since the PD98411 operates on 3.3 V, a coupling circuit should be added if it is to be connected to a 5-V device. PD98411 Port0 3.3V 0.1F 510 510 110 110 82 5V 82 430 430 GND RDIT0 RDIC0 TDOT0 TDOC0 820 820 91 91 5V optical transceiver RSDT RSDC TXDT TXDC 0.1Fx4 5V 130 130 1.1k 1.1k 0.1F GND SD0 PECL->TTL translator MC10H350 by Motorola, etc. GND GND VCCR VCCT VEER VEET SD 4 Data Sheet S12953EJ4V0DS00 PD98411 3) UTOPIA Interface The UTOPIA interface transfers transmit/receive cell data to a device in the upper ATM layer. version 1.0 June '95" standard. Bus Mode Dual eight-bit bus. In this mode, an 8-bit data bus is used for two ports. Ports 0 and 1 transfer signals using one eight-bit bus, while ports 2 and 3 transfer signals using another eight-bit bus. The ports operate independently. The way to indicate Cell Available state One TCLAV & one RCLAV signal mode The one TCLAV & one RCLAV signal mode outputs the TCLAV and RCLAV signal status information for four ports of the PD98411 by multiplexing them into a single signal. PD98411 Port0 TCLAV RCLAV Port1 TDI The interface between the PD98411 and the ATM layer conforms to "MPHY Data Path Operation" of the "UTOPIA Level 2 PMD PD98411 Port0 UTOPIA 8-bit ATM layer device Port1 ATM layer Device Port2 8-bit Port3 ATM layer device Port2 8 or 16-bit RDO Port3 TADD RADD Single eight-bit bus. In this mode, cell data for all four ports is transferred through an eight-bit bus. The maximum transfer rate is 400 Mbps (8 bits x 50 MHz). Direct Status Indication Mode PD98411 has four TXCLAV and RXCLAV status signals, one pair of TXCLAV and RXCLAV for each port. Status signals and cell transfers are independent of each other. No address information is needed to obtain status information. PMD PD98411 Port0 Port1 UTOPIA Port0 TCLAV3-TCLAV0 Port1 8-bit Port2 Port3 ATM layer device PD98411 Port2 RCLAV3-RCLAV0 TDI 8 or 16-bit RDO ATM layer Device Port3 TADD RADD Single sixteen-bit bus. In this mode, cell data for all four ports is transferred through a sixteen-bit bus. The maximum transfer rate is 800 Mbps (16 bits x 50 MHz). Multiplexed Status Polling Mode When six or more PD98411s are connected to one ATM layer, ATM layer obtain the status information of all the connected ports in the 53 clock cycles in which it transmits or receives a PMD PD98411 Port0 Port1 single data cell. Because a minimum of two clock cycles are UTOPIA required to obtain the TCLAV/RCLAV signal status of a port by ATM layer polling. Therefore every port address is allocated in a fixed manner to one of the four status signals and to one of eight 16-bit Port2 Port3 ATM layer device port groups. Data Sheet S12953EJ4V0DS00 5 6 155.52 MHz PECL serial interface Conforms to UTOPIA level 2 multi-PHY interface of 400 to 800 Mbps Clock Recovery BLOCK DIAGRAM S/P Rx framer block Rx timing generation Descramble BIP generation Overhead extraction Tx framer block Scramble Tx timing generation BIP generation Overhead setup Rx ATM cell processor block Cell descramble Cell synchronization Idle cell drop HEC compare/control Port0 ATM layer interface Data Sheet S12953EJ4V0DS00 PMD interface (PECL IN/OUT) Port1 PMD interface (PECL IN/OUT) RX FIFO (8 cells) P/S Tx ATM cell processor block HEC generation Cell scramble Cell mapping Idle cell insertion TX FIFO (8 cells) Clock Recovery PMD interface (PECL IN/OUT) S/P Rx framer block S/PTX Framer Block block Rx framer Clock P/S recovery Rx ATM cell processor block RX FIFO Clock P/S recovery PMD interface (PECL IN/OUT) Tx ATM Cells Operate Block Rx ATM cell processor block Tx FIFO 6 Cells RX FIFO S/PTX Framer Block Rx framer block P/S Tx framer block Tx ATM Cells Operate Block Rx ATM cell processor block Tx FIFO 6 Cells RX FIFO Port2 Tx ATM cell processor block TX FIFO Port3 Clock Synthesizer OAM sequencer Mode registers Test registers Performance registers Interrupt cause registers JTAG Tx/Rx overhead registers Management interface PD98411 CPU Bus Interface Address: 9 bits Data: 8 bits PD98411 FUNCTIONAL PIN GROUPS JRSTB JDO JMS JTAG boundary scan interface JCK +3.3 V VDD GND RCLK1 RCLK2 RENBL1_B RENBL2_B RCLAV0 RCLAV1 RCLAV2 RCLAV3 RADD1[4:0] RADD2[4:0] RSOC1 RSOC2 RDO[15:0] RPR1 RPR2 RDIT0/RDIC0 (differential input) TDOT0/TDOC0 (differential input) RDIT1/RDIC1 (differential input) TDOT1/TDOC1 (differential input) PMD interface RDIT2/RDIC2 (differential input) TDOT2/TDOC2 (differential input) RDIT3/RDIC3 (differential input) TDOT3/TDOC3 (differential input) TFKT/TFKC (differential input) REFCLK REFCLK-2nd CSSEL RXFP TXFP TFSS RCL TCL XLFC MADD[8:0] MDATA[7:0] CS_B DS/RD_B Management interface RW/WR_B ACK/RDY_B BMODE RESET_B PHINT0_B PHINT1_B PHINT2_B PHINT3_B SD3 SD2 SD1 SD0 PALM0[2:0] PALM1[2:0] PALM2[2:0] PALM3[2:0] Alarm signal output CMD0 CMD1 CMD2 CMD3 External alarm signal input TCLK1 TCLK2 TENBL1_B TENBL2_B TCLAV0 TCLAV1 TCLAV2 TCLAV3 TADD1[4:0] TADD2[4:0] TSOC1 TSOC2 TDI[15:0] TPR1 TPR2 JDI UTOPIA interface (Rx) UTOPIA interface (Tx) SD signal input Data Sheet S12953EJ4V0DS00 7 PD98411 PIN CONFIGURATION 240-pin plastic QFP (fine pitch) (32 x 32 mm) (Top View) Remark1. 2. IC: internal connect pin. Leave the IC pins open. In this document, xxx_B stands for active low pin. 8 Data Sheet S12953EJ4V0DS00 PD98411 PIN ARRANGEMENT TABLE (1/2) Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Pin Name GND GND RDO[11] RDO[12] RDO[13] RDO[14] RDO[15] VDD RCLAV1 RCLAV0 GND RCLK1 RENBL1_B VDD RADD1[0] RADD1[1] RADD1[2] RADD1[3] RADD1[4] GND VDD ACK/RDY_B RW/WR_B DS/RD_B CS_B MADD[8] MADD[7] MADD[6] MADD[5] MADD[4] MADD[3] MADD[2] MADD[1] MADD[0] GND MD[7] MD[6] MD[5] MD[4] Number 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 Pin Name VDD GND MD[3] MD[2] MD[1] MD[0] VDD BMODE IC RCL GND VDD-PEC TFKC TFKT GND-PEC CSSEL GND-CS VDD-CS REFCLK JCK GND VDD GND REFCLK-2nd JDO JDI JMS JRST_B VDD-PE0 TDOT0 TDOC0 GND-PE0 GND-PE0 RDIC0 RDIT0 VDD-PE0 XLFC VDD-PE1 TDOT1 Number 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 Pin Name TDOC1 GND VDD GND-PE1 GND-PE1 RDIC1 RDIT1 VDD-PE1 IC VDD-PE2 TDOT2 TDOC2 GND-PE2 GND-PE2 RDIC2 RDIT2 VDD-PE2 IC VDD-PE3 TDOT3 TDOC3 VDD GND GND-PE3 GND-PE3 RDIC3 RDIT3 VDD-PE3 GND IC IC IC IC IC IC IC IC SD0 SD1 Number 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 Pin Name SD2 SD3 VDD GND GND IC TCL TXFP RXFP TFSS CMD3 CMD2 CMD1 CMD0 VDD PALM3[2] PALM3[1] PALM3[0] PALM2[2] PALM2[1] PALM2[0] GND VDD PALM1[2] PALM1[1] PALM1[0] PALM0[2] PALM0[1] PALM0[0] VDD GND PHINT3_B PHINT2_B PHINT1_B PHINT0_B RESET_B GND TADD2[0] TADD2[1] Data Sheet S12953EJ4V0DS00 9 PD98411 (2/2) Number 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 Pin Name TADD2[2] TADD2[3] TADD2[4] VDD GND TENBL2_B TCLK2 VDD TCLAV3 TCLAV2 GND TDI[0] TDI[1] TDI[2] TDI[3] TDI[4] VDD TDI[5] TDI[6] TDI[7] TPR2 TSOC2 Number 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 Pin Name GND GND VDD TADD1[0] TADD1[1] TADD1[2] TADD1[3] TADD1[4] VDD GND TENBL1_B TCLK1 GND TCLAV1 TCLAV0 VDD TDI[8] TDI[9] TDI[10] TDI[11] TDI[12] GND Number 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 Pin Name VDD TDI[13] TDI[14] TDI[15] TPR1 TSOC1 GND VDD RSOC2 RPR2 RDO[0] RDO[1] RDO[2] VDD RDO[3] RDO[4] RDO[5] RDO[6] RDO[7] VDD GND RCLAV3 Number 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 Pin Name RCLAV2 GND RCLK2 RENBL2_B VDD RADD2[0] RADD2[1] RADD2[2] RADD2[3] RADD2[4] GND VDD RSOC1 RPR1 RDO[8] RDO[9] RDO[10] VDD 10 Data Sheet S12953EJ4V0DS00 PD98411 PIN NAME ACK/RDY_B BMODE CMD3-CMD0 CS_B CSSEL DS/RD_B GND GND-CS GND-PE3, GND-PE2, GND-PE1, GND-PE0 GND-PEC JCK JDI JDO JMS JRST_B MADD[8:0] MD[7:0] PALM3[2:0], PALM2[2:0], PALM1[2:0], PALM0[2:0] PHINT3_B, PHINT2_B, PHINT1_B, PHINT0_B, RADD2[4:0], RADD1[4:0] RCL : Internal Receive System Clock : Receive Address : Physical Interrupt : Ground for TFKT/C PECL Block : JTAG Clock : JTAG Data Input : JTAG Data Output : JTAG Mode Select : JTAG Reset : Management Interface Address Bus : Management Interface Data Bus : Physical Alarm Output Signals TDOC3-TDOC0 TDOT3-TDOT0 TENBL2_B, TENBL1_B TFKC TFKT TFSS TPR2,TPR1 TSOC2,TSOC1 TxFP VDD VDD-CS VDD-PE3, VDD-PE2, VDD-PE1, VDD-PE0 VDD-PEC : Supply Voltage for TFKT/C PECL Block XLFC : Tx Loop Filter Capacity : Transmit Reference Clock Complement : Transmit Reference Clock True : Transmit Frame Set Signal : Transmit Data Path Parity : Transmit Start Of Cell : Transmit Frame Pulse : Supply Voltage : Supply Voltage for Analog PLL Block : Supply Voltage for Rx PECL Block : Acknowledge/Ready : Bus Mode : Command Signal : Chip Select : Clock Source Select : Data Strobe/Read : Ground : Ground for Analog PLL Block : Ground for Rx PECL Block REFCLK REFCLK-2nd RENBL2_B, RENBL1_B RESET_B RPR2, RPR1 : System Reset : Receive Data Path Parity : System Clock : 2nd Reference Cock : Receive Data Enable RSOC2, RSOC1 : Receive Start Of Cell RW/WR_B RxFP SD3-SD0 TADD2[4:0], TADD1[4:0] TCL : Internal Transmit System Clock : Management Interface Read/Write : Receive Frame Pulse : Signal Detect : Transmit Address TCLAV3-TCLAV0 : Transmit Cell Available Signals TCLK2, TCLK1 TDI15-TDI0 : Transmit DATA transferring Clock : Transmit Data Input from the ATM Layer : Transmit Data Output Complement : Transmit Data Output True : Transmit Data Enable RCLAV3-RCLAV0 : Receive Cell Available Signals RCLK2, RCLK1 RDIC3-RDIC0 RDIT3-RDIT0 RDO[15:0] : Receive Data Transferring Clock : Receive Data Input Complement : Receive Data Input True : Receive Data Output Data Sheet S12953EJ4V0DS00 11 PD98411 CONTENTS 1. PIN FUNCTIONS .............................................................................................. 13 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.10 PMD Interface ............................................................................................................... UTOPIA Interface .......................................................................................................... Management Interface ................................................................................................... Alarm Signal Input/output ................................................................................................ JTAG Boundary Scan .................................................................................................... Power Supply and Ground ...............1 Others ........................................................................................................................ Disipation of Unused Pins ............................................................................................... Initial State of Pins ........................................................................................................ Correspondence between UTOPIA Interface Modes and Pins Used ......................................... 13 15 19 20 20 21 21 22 23 24 2. ELECTRICAL CHARACTERISTICS ....................................................................... 25 3. PACKAGE DRAWING .......................................................................................... 33 4. RECOMMENDED SOLDERING CONDITIONS ......................................................... 34 12 Data Sheet S12953EJ4V0DS00 PD98411 1. PIN FUNCTIONS 1.1 PMD Interface Pin Name RDIT3RDIT0 RDIC3RDIC0 TDOT3TDOT0 TDOC3TDOC0 SD3-SD0 Pin No. 105, 94, 85, 74 104, 93, 84, 73 98, 89, 78, 69 99, 90, 79, 70 119-116 I/O Level P-ECL True(+) P-ECL Complement(-) P-ECL True(+) P-ECL Complement(-) CMOS I Line signal detection signal input. Refers to the pins for inputting the SD (Signal Detect) signal of line transceivers (such as optical modules). If this signal goes low, this port detects LOS. High: Normal REFCLK 58 CMOS I System clock (19.44MHz) input. Used as the source clock for the internal synthesizer PLL/clock recovery PLL and register operation. REFCLK-2nd 63 CMOS I Second system clock (19.44MHz) input. Refers to the pin for inputting the second source clock of the internal synthesizer PLL. This pin is not used if it is unnecessary to switch the source clock of the synthesizer PLL. The CSSC register (address 076H) specifies which of REFCLK and REFCLK-2nd clocks to use as the source block. The REFCLK input is selected as the default. Even when REFCLK-2nd is used as the source clock of the synthesizer PLL, REFCLK is used for register operation as well; therefore, it is necessary to input the clock. Low: LOS state O O Transmit serial data output. Refers to the differential output of the P-ECL level. To the transmit clock. I I/O I Receive serial data input. Refers to the differential input of the P-ECL level. Function (1/3) REFCLK REFCLK_2nd Transmit synthesizer PLL clock 155.52MHz transmit clock Register REF_cnt bit RXFP 126 CMOS O Receive frame pulse output (8kHz). The pulse signal is output synchronously with the start of the receiving frame. The pulse signal is 1 cycle of the RCL clock in length. The internal FPMSK register (address: 07CH) is used to select which of the four ports will output the pulse synchronous to the receiving frame. No port is selected as the default; therefore, using the default will result in no output. Data Sheet S12953EJ4V0DS00 13 PD98411 (2/3) Pin Name XLFC Pin No. 76 I/O Level Analog I/O O Function Loop filter capacity connection pin. Refers to the pin connecting the loop filter of the synthesizer PLL. Leave the pin open. TXFP 125 CMOS O Transmitting end frame pulse signal output (8KHz). Outputs a pulse signal synchronous with the start of the transmission frame and equivalent to the 1 cycle of the TCL clock in length. The setting of the internal FPMSK register (address: 07CH) selects which of the four ports should output the pulse synchronous with the transmitting frame. No port is selected as the default value; therefore, using the default will result in no output. TFSS 127 CMOS I Frame transmission disable signal input. If High is input to this pin, the output data strings of all ports are fixed to either to 0 or 1 and frame transmission stops. If Low is input, transmission restarts from the start (the 1st A1 byte) of the frame. Transmission starts with the output of a transmission synchronously with the rising edge of the TCL clock 9 cycles after the last rising edge of the TCL clock at which TFSS was detected as being high. RCL 49 CMOS O Receive system clock output (19.44MHz). Each port uses the 155.52MHz receive clock divided by eight for internal receive processing; and this pin outputs this clock. Which port's system clock is output is selected by setting the relevant value of the RCMSK register (address: 07BH). By using the default value, the clock of port 0 is selected. During resetting or when no port is selected, Low is output. Also, this pin can output REFCLK-2nd clock. 14 Data Sheet S12953EJ4V0DS00 PD98411 # # # # # # # # # # # (3/3) Pin Name TCL Pin No. 124 I/O Level CMOS I/O O Function Transmission system clock output (19.44 MHz). Each port uses the 155.52MHz transmit clock divided by eight for internal transmit processing; and this pin outputs this clock. Which port's system clock is output is selected by setting the relevant value of the TCMSK register (address: 07AH). During resetting or when no port is selected, Low is output. TFKT 53 P-ECL True(+) TFKC 52 P-ECL Complement(-) CSSEL 55 CMOS I I I Externally generated 155.52MHz transmit clock input. Refers to the pin for inputting the externally generated transmit clock (155.52MHz) when not using the internally mounted synthesizer PLL. This pin is enabled by setting the CSSEL pin to High. TFKT/TFKC pin enable signal input. This pin inputs the enable signal of the TFKT/TFKC pin when inputting a 155.52MHz clock from outside the chip at the TFKT/TFKC pin. High: TFKT/TFKC pin enable Low: TFKT/TFKC pin disable 1.2 UTOPIA Interface The pin used for each UTOPIA interface signal varies with the mode selected by the internal MltUt register (at address 079H). Please refer the table "Correspondence between UTOPIA Interface Modes and Pins Used". (1/4) Pin Name RDO[15:8] RDO[7:0] Pin No. 7-3 239-237 219-215 213-211 I/O Level CMOS I/O O 3-state Receive data buses. These 16-bit data bus pins transfer receive data to the ATM layer device. Output is made synchronous with the startup of the RCLK clock. The pins used varies depending on the UTOPIA interface mode selected by the MltUt register (address: 079H). * Single 8-bit bus: RDO[7:0] * Single 16-bit bus: RDO[15:0] * Dual 8-bit bus: RDO[15:8]/RDO[7:0] RCLK2 RCLK1 225 12 CMOS I Receive clock input. These pins accept receive data transfer clocks of up to 50MHz. The pin to be used varies depending on the UTOPIA interface mode selected by the MltUt register (address: 079H). * Single 8-bit bus: RCLK2 * Single 16-bit bus: RCLK1 * Dual 8-bit bus: RCLK1/RCLK2 Function Data Sheet S12953EJ4V0DS00 15 PD98411 (2/4) Pin Name RSOC2 RSOC1 Pin No. 209 235 I/O Level CMOS I/O O 3-state Function Receive cell starting location signal output. These pins output a signal which indicates the location of the first byte with regard to the ATM layer device. The pin to be used varies depending on the UTOPIA interface mode selected by the MltUt register (address: 079H). * Single 8-bit bus: RSOC2 * Single 16-bit bus: RSOC2 * Dual 8-bit bus: RSOC1/RSOC2 RENBL2_B RENBL1_B 226 13 CMOS I Receive enable signal input. These pins input a signal which indicates that the corresponding ATM layer device is capable of accepting receive data. The pin to be used varies depending on the UTOPIA interface mode selected by the MltUt register (address: 079H). * Single 8-bit bus: RENBL2_B * Single 16-bit bus: RENBL1_B * Dual 8-bit bus: RENBL1_B/RENBL2_B RCLAV3 RCLAV2 RCLAV1 RCLAV0 222 223 9 10 CMOS O 3-state Receive cell transferable signal output. This signal informs the ATM layer device that 1 cell or more of data exists in the receive FIFO. In 1TCLAV&1RCLAV mode, the RCLAV signal of each port is internally multiplexed to be output as a signal. Of the four signals of RCLAV0 to RCLAV3, the pin and operation of the signal which is used vary depending on the UTOPIA interface mode selected by the MltUt register (address: 079H). * Single 8-bit bus: RCLAV2 * Single 16-bit bus: RCLAV1 * Dual 8-bit bus: RCLAV1/RCLAV2 In Direct Status Indication (DSI) mode, the four signals of RCLAV0 to RCLAV3 are allocated to each of the ports to identify their FIFO statuses. RCLAV0 corresponds to Port 0, and RCLAV3 to Port 3. RADD2[4:0] RADD1[4:0] 232-228 19-15 CMOS I Receiving end PHY address input. These pins input the address which selects the port. Different pins are used depending on the UTOPIA interface mode selected by the MltUt register (address: 079H). * Single 8-bit bus: RADD2[4:0] * Single 16-bit bus: RADD1[4:0] * Dual 8-bit bus: RADD1[4:0]/RADD2[4:0] 16 Data Sheet S12953EJ4V0DS00 PD98411 (3/4) Pin Name RPR2 RPR1 Pin No. 210 236 I/O Level CMOS I/O O Parity bit output pins. Odd parity bits are generated and output from these pins with respect to the data output from RDO15-RDO0. The pin to be used varies depending on the UTOPIA interface mode selected by the MltUt register (address: 079H). * Single 8-bit bus: RPR2 * Single 16-bit bus: RPR2 * Dual 8-bit bus: RPR1/RPR2 TDI[15:8] TDI[7:0] 204-202 199-195 176-174 172-168 CMOS I Transmit data buses. These data buses input transmit data from the ATM layer device at the rising edge of the TCLK clock. The pin to be used varies depending on the UTOPIA interface mode selected by the MltUt register (address: 079H). * Single 8-bit bus: TDI[15:8] * Single 16-bit bus: TDI[15:0] * Dual 8-bit bus: TDI[15:8]/TDI[7:0] TCLK2 TCLK1 163 190 CMOS I Transmit clock input. These pins input clocks of up to 50MHz for transmit data transfer. The pin to be used varies depending on the UTOPIA interface mode selected by the internal MltUt register (address: 079H). * Single 8-bit bus: TCLK1 * Single 16-bit bus: TCLK2 * Dual 8-bit bus: TCLK1/TCLK2 TSOC2 TSOC1 178 206 CMOS I Transmit cell starting location signal input. These pins input a signal which indicates the location of the first byte of the transmit cell. The pin to be used varies depending on the UTOPIA interface mode selected by the MltUt register (address: 079H). * Single 8-bit bus: TSOC1 * Single 16-bit bus: TSOC1 * Dual 8-bit bus: TSOC1/TSOC2 TENBL2_B TENBL1_B 162 189 CMOS I Transmit enable signal input. These pins input a signal which indicates that the ATM layer device is outputting valid transmit data to TDI[15]-TDI[0]. The pin to be used varies depending on the UTOPIA interface mode selected by the internal MltUt register (address: 079H). * Single 8-bit bus: TENBL1_B * Single 16-bit bus: TENBL2_B * Dual 8-bit bus: TENBL1_B/TENBL2_B Function Data Sheet S12953EJ4V0DS00 17 PD98411 (4/4) Pin Name TCLAV3 TCLAV2 TCLAV1 TCLAV0 Pin No. 165 166 192 193 I/O Level CMOS I/O O 3-state Function Transmit cell acceptable signal output. The signal informs the ATM layer device that unused storage space of at least 1 cell is available in the transmit FIFO. In 1TCLAV&1RCLAV mode, the TCLAV signal of each port is internally multiplexed to be output as a signal. Of the four signals of TCLAV0 to TCLAV3, the pin to be used varies depending on the UTOPIA interface mode selected by the MltUt register (address: 079H). * Single 8-bit bus: TCLAV1 * Single 16-bit bus: TCLAV2 * Dual 8-bit bus: TCLAV1/TCLAV2 In Direct Status Indication (DSI) mode, the four pins TCLAV0 to TCLAV3 are allocated to each of the ports signal by signal, and indicate the FIFO statuses of each port. TCLAV0 corresponds to Port 0; and TCLAV3 to Port 3. TADD2[4:0] TADD1[4:0] 159-155 186-182 CMOS I Transmission PHY address input. These pins input the address of the port to be selected. The pins used vary depending on the UTOPIA interface mode selected by the MltUt register (address: 079H). * Single 8-bit bus: TADD1[4:0] * Single 16-bit bus: TADD2[4:0] * Dual 8-bit bus: TADD1[4:0]/TADD2[4:0] TPR2 TPR1 177 205 CMOS I Parity bit input pins. These pins input the odd parity bit input from TD0[15]-TDO[0]. The pin to be used varies depending on the UTOPIA interface mode selected by the MltUt register (address: 079H). * Single 8-bit bus: TPR1 * Single 16-bit bus: TPR1 * Dual 8-bit bus: TPR1/TPR2 18 Data Sheet S12953EJ4V0DS00 PD98411 1.3 Management Interface Pin Name BMODE Pin No. 47 I/O Level CMOS I/O I Mode selection input. This pin input is used to select the mode of the management interface. BMODE=: 1: Selects When BMODE=1, the pin functions as WR_B selecting Write for Data Sheet S12953EJ4V0DS00 19 PD98411 1.4 Alarm Signal Input/output Pin Name CMD0-CMD3 Pin No. 128-131 I/O Level CMOS I/O I Function General-purpose input signal. Refers to the general-purpose input pins which input the status signals, etc. from external peripheral devices. The signal level of these pins can also be reflected in the status bits of internal registers, and changes in these bits can be used identify interrupt factors. Each port is equipped with a pin: CMD0 corresponds to Port 0 and CMD3 to Port 3. PALM3[2:0] PALM2[2:0] PALM1[2:0] PALM0[2:0] 133-135 136-138 141-143 144-146 CMOS O PHY layer alarm detection signal output. These pins output the signal to notify that the port detected the alarm or the defect (LOS, OOF, LOF, LOP OCD, LCD, Line AIS, , Path AIS, Line RDI, Path RDI) or that the level of the CMD pin input was changed. Additionary, it is possible to use as the general output ports which reflects state of the bit of the internal register,too. The events to be indicated are selected by seting to AMPR, AMR1, AMR2 registers. 1.5 JTAG Boundary Scan Pin Name Pin No. 65 I/O Level CMOS I/O I Function Refers to the boundary scan data input. When unused, connect this to ground. JDI JDO 64 CMOS O 3-state Refers to the boundary scan data output. When unused, leave this open. Refers to the boundary scan clock input. When unused, connect this to ground. JCK 59 CMOS I JMS 66 CMOS I Refers to the boundary scan mode select signal input. When unused, connect this to ground. JRST_B 67 CMOS I Refers to the boundary scan reset signal input. When unused, connect this to ground. 20 Data Sheet S12953EJ4V0DS00 PD98411 1.6 Power Supply and Ground Pin No 8, 14, 21, 40, 46, 61, 81, 100, 120, 132, 140, 147, 160, 164, 173, 181, 187, 194, 201, 208, 214, 220, 227, 234, 240 GND 1 ,2, 11, 20, 35, 41, 50, 60, 62, 80, 101, 107, 121, 122, 139, 148, 154, 161, 167, 179, 180, 188, 191, 200, 207, 221, 224, 233 VDD-PEC GND-PEC 51 54 --TFKT/TFKC input high-speed part power supply (+3.3V5%) and ground. Noise from this power supply affects the jitter characteristic. Eliminate noise through countermeasures such as filters. VDD-CS GND-CS 57 56 --Transmit clock synthesizer PLL power supply (+3.3V5%) and ground. Noise from this power supply affects the jitter characteristic. Eliminate noise through countermeasures such as filters. VDD-PE3 VDD-PE2 VDD-PE1 VDD-PE0 GND-PE3 GND-PE2 GND-PE1 GND-PE0 97, 106 88, 95 77, 86 68, 75 102, 103 91, 92 82, 83 71, 72 --Each port high-speed section, receive clock recovery section power supply (+3.3V5%). Noise from this power supply affects the jitter characteristic. Eliminate noise through countermeasures such as filters. Each port high-speed section, receive clock recovery section ground. Noise from this power supply affects the jitter characteristic. Eliminate noise through countermeasures such as filters. -I/O -Function Low-speed section logic power supply (+3.3V5%) and ground. Pin Name VDD 1.7 Others Pin Name Pin No. 48, 87, 96, 108-115 123 I/O Level CMOS I/O -Function These refer to the internal circuit connection test pins. Be sure to leave them open. IC Data Sheet S12953EJ4V0DS00 21 PD98411 1.8 Disipation of Unused Pins Take the following actions with pins that are unused in certain modes. Pin Name RCLK2, RCLK1 RENBL2_B, RENBL1_B RADD2[4:0], RADD1[4:0] TDI[15:0] TCLK2, TCLK1 TSOC2, TSOC1 TENBL2_B, TENBL1_B TADD2[4:0], TADD1[4:0] TPR2, TPR1 RDO[15:0] RSOC2, RSOC1 RPR2, RPR1 RCLAV3-RCLAV0 TCLAV3-TCLAV0 CMD3-CMD0 SD3-SD0 TFKT/TFKC TFSS XLFC REFCLK-2nd Each of output pins Connect them to ground. Pull them up. Pull up TFKT and connect TFKC to ground. Connect it to ground. Leave it open. Connect it to ground Leave them open. Leave them open. Measure Connect them to ground. 22 Data Sheet S12953EJ4V0DS00 PD98411 1.9 Initial State of Pins Pin Name RDO[15:0] RSOC2, RSOC1 RCLAV3-RCLAV0 TCLAV3-TCLAV0 RPR2, RPR1 PHINT3_B-PHINT0_B PALM3[2:0]-PALM0[2:0] RXFP TXFP TCL RCL MD[7:0] ACK/RDY_B TDOT3-TDOT0 TDOC3-TDOC0 H L L L L L Hi-Z H L H H L L L L L Hi-Z H L H During Resetting Hi-Z After Resetting Hi-Z Data Sheet S12953EJ4V0DS00 23 PD98411 1.10 Dual 8-bit Rx Direct Status Indication Using 4 TCLAV/ 4 RCLAV signals (two-state outputs) 0101 Tx Correspondence between UTOPIA Interface Modes and Pins Used Mode MSL[3:0] 0001 Tx Port 0/1 Port 2/3 Port 0/1 Port 2/3 Port 0/1 Port 2/3 Rx Port 0/1 Port 2/3 Pins Used (_B is omitted) TCLK1, TDI[15:8], TADD1, TPR1, TENBL1_B, TCLAV1, TSOC1 TCLK2, TDI[7:0], TADD2, TPR2, TENBL2_B, TCLAV2, TSOC2 RCLK1, RDO[15:8], RADD1, RPR1, RENBL1_B, RCLAV1, RSOC1 RCLK2, RDO[7:0], RADD2, RPR2, RENBL2_B, RCLAV2, RSOC2 TCLK1, TDI[15:8], TADD1, TPR1, TENBL1_B, TCLAV0-TCLAV1, TSOC1 TCLK2, TDI[7:0], TADD2, TPR2, TENBL2_B, TCLAV2-TCLAV3, TSOC2 RCLK1, RDO[15:8], RADD1, RPR1, RENBL1_B, RCLAV0-RCLAV1, RSOC1 RCLK2, RDO[7:0], RADD2, RPR2, RENBL2_B, RCLAV2-RCLAV3, RSOC2 TCLK1, TDI[15:8], TADD1, TPR1, TENBL1_B, TCLAV1, TSOC1 TCLK2, TDI[7:0], TADD2, TPR2, TENBL2_B, TCLAV2, TSOC2 RCLK1, RDO[15:8], RADD1, TPR1, RENBL1_B, RCLAV1, RSOC1 RCLK2,RDO[7:0], RADD2, TPR2, RENBL2_B, RCLAV2, RSOC2 TCLK1, TDI[15:8], TADD1, TPR1, TENBL1_B, TCLAV0-TCLAV1, TSOC1 TCLK2, TDI[7:0], TADD2, TPR2, TENBL2_B, TCLAV2-TCLAV3, TSOC2 RCLK1, RDO[15:8], RADD1, RPR1, RENBL1_B, RCLAV0-RCLAV1, RSOC1 RCLK2, RDO[7:0], RADD2, RPR2, RENBL2_B, RCLAV2-RCLAV3, RSOC2 2 TCLAV/2 RCLAV Multiplexed Status Polling Using 2 TCLAV/ 2 RCLAV signals (three-state outputs) Multiplexed Status Polling Using 4 TCAV/ 4 RCLAV signals (three-state outputs) 1001 Tx Rx Port 0/1 Port 2/3 Port 0/1 Port 2/3 Port 0/1 Port 2/3 1101 Tx Rx Port 0/1 Port 2/3 Single 8-bit 1 TCLAV/1 RCLAV Direct Status Indication Using 4 TCLAV/ 4 RCLAV signals (two-state outputs) Multiplexed Status Polling Using 4 TCLAV/ 4 RCLAV signals (three-state outputs) Multiplexed Status Polling Using 4 TCAV/ 4 RCLAV signals (three-state outputs) 0010 0110 Tx Rx Tx Rx TCLK1, TDI[15:8], TADD1, TPR1, TENBL1_B, TCLAV1, TSOC1 RCLK2, RDO[7:0], RADD2, RPR2, RENBL2_B, RCLAV2, RSOC2 TCLK1, TDI[15:8], TADD1, TPR1, TENBL1_B, TCLAV0-TCLAV3, TSOC1 RCLK2, RDO[7:0], RADD2, RPR2, RENBL2_B, RCLAV0-RCLAV3, RSOC2 TCLK1, TDI[15:8], TADD1, TPR1, TENBL1_B, TCLAV1, TSOC1 RCLK2, RDO[7:0], RADD2, RPR2, RENBL2_B, RCLAV2, RSOC2 TCLK1, TDI[15:8], TADD1, TPR1, TENBL1_B, TCLAV0-TCLAV3, TSOC1 RCLK2, RDO[7:0], RADD2, RPR2, RENBL2_B, RCLAV0-RCLAV3, RSOC2 TCLK2, TDI[15:0], TADD2, TPR1, TENBL2_B, TCLAV2, TSOC1 RCLK1, RDO[15:0], RADD1, RPR2, RENBL1_B, RCLAV1, RSOC2 TCLK2, TDI[15:0], TADD2, TPR1, TENBL2_B, TCLAV0-TCLAV3, TSOC1 RCLK1, RDO[15:0], RADD1, RPR2, RENBL1_B, RCLAV0-RCLAV3, RSOC2 TCLK2, TDI[15:0], TADD2, TPR1, TENBL2_B, TCLAV2, TSOC1 RCLK1, RDO[15:0], RADD1, RPR2, RENBL1_B, RCLAV1, RSOC2 TCLK2, TDI[15:0], TADD2, TPR1, TENBL2_B, TCLAV0-TCLAV3, TSOC1 RCLK1, RDO[15:0], RADD1, RPR2, RENBL1_B, RCLAV0-RCLAV3, RSOC2 1010 Tx Rx 1110 Tx Rx Single 16-bit 1 TCLAV/1 RCLAV Direct Status Indication Using four TCLAV/four RCLAV signals (two-state outputs) Multiplexed Status Polling Using one TCLAV/one RCLAV signal (three-state outputs) Multiplexed Status Polling Using four TCLAV/four RCLAV signals (three-state outputs) 0011 0111 Tx Rx Tx Rx 1011 Tx Rx 1111 Tx Rx 24 Data Sheet S12953EJ4V0DS00 PD98411 2. ELECTRICAL CHARACTERISTICS Note The `S' mark shows the characteristics which was changed from previous version. Absolute Maximum Ratings Parameter Supply voltage Input/output voltage Symbol VDD VI/VO Topt Tstg Pins except on P-ECL VIA/VOA P-ECL pins Conditions Rating -0.5 to +4.6 -0.5 to +6.6 and VDD+3.0 -0.5 ~ +4.6 and VDD+0.5 -40 to +85 -65 to +150 Unit V V V C C S Operating temperature Storage temperature Caution If even one of the parameters exceeds its absolute maximum rating even momentarily, the quality of the product may be degraded. The absolute maximum rating therefore specifies the upper or lower limit of the values at which the product can be used without physical damage. Be sure not to exceed or fall below these values when using the product. Capacitance Parameter Input capacitance Output capacitance I/O capacitance Symbol CI CO CIO Conditions Frequency = 1MHz Frequency = 1MHz Frequency = 1MHz MIN. TYP . 6 6 6 MAX. 10 10 10 Unit pF pF pF Recommended Operating Conditions Parameter Symbol VDD TA VIL VILA High-level input voltage VIH VIHA P-ECL differential input voltage VIDIFF Pins except on P-ECL P-ECL pins Pins except on P-ECL P-ECL pins P-ECL pins Conditions MIN. VDD x 0.95 -40 0 VDD -2.82 2.2 VDD -1.49 0.1 TYP . 3.3 MAX. VDD x 1.05 +85 0.8 VDD -1.50 5.25 VDD -0.4 2.41 Unit V C V V V V V S S Supply voltage Operating ambient temperature Low-level input voltage S S Data Sheet S12953EJ4V0DS00 25 PD98411 S DC Characteristics (VDD = 3.3 5% V, TA = -40 to +85 C) Parameter Off-state output current Input leakage current Symbol IOZ IIL IILA Conditions VI = VDD or GND Pins except on P-ECL VI = VDD or GND P-ECL pins 59,65,66,67 pins P-ECL pins RL = 50, VT = VDD -2V High-level output voltage Low-level output current VOHA IOL IOH IDD P-ECL pins RL = 50, VT = VDD -2V VOL = 0.4V, VDD = 3.3V Pins except on P-ECL High-level output current Supply current VOH = 2.4V, VDD = 3.3V Pins except on P-ECL During normal operation 500 800 mA -9.0 mA 9.0 mA VDD -1.14 VDD -0.92 VDD -0.69 V 5.4 30 10 56.4 MIN. TYP . MAX. 10 10 Unit A A A K V S Internal Pull-down resistance Low-level output voltage RPL VOLA VDD -2.175 VDD -1.975 VDD -1.755 S S S AC Characteristics (VDD = 3.3 5% V, TA = -40 to +85 C) The propagation delay time is defined as follows: 0.7VDD Input pin 0.3VDD 0.5VDD Output pin 0.5VDD tPD AC Testing Load Circuit AC Test Device Under Test CL CL=30pF CL Include Jig Capacitance S S Remark In case of CL=50pF, the operating condition changes to TA = 0 to +70 C. 26 Data Sheet S12953EJ4V0DS00 PD98411 Management Interface a) Internal Register Read Parameter CS_B setting time (vs. DS_B[RD_B]) R/W_B[WR_B] setting time (vs. DS_B[RD_B]) Address hold time (vs. DS_B[RD_B]) CS_B hold time (vs. DS_B[RD_B]) R/W_B[WR_B] hold time (vs. DS_B[RD_B]) tHADDS tHCSDS tHRWDS tVAKDS tVDADS tIAKDS tIDADS tDDAAK tWDS tDSINT Load capacitance: 30 pF Load capacitance: 30 pF Load capacitance: 30 pF Load capacitance: 30 pF Load capacitance: 30 pF 51.44 51.44 10 15 4 0 0 15 25 70 70 10 ns ns ns ns ns ns ns ns ns ns Symbol tSCSDS tSRWDS Conditions MIN. 10 5 5 TYP . MAX. Unit ns ns ns Address setting time (vs. DS_B[RD_B]) tSADDS S S S S S DS_B[RD_B] ACK_B[RDY_B] output delay DS_B[RD_B] data output delay DS_B[RD_B] ACK_B[RDY_B] float delay DS_B[RD_B] data float delay ACK_B data output delay DS_B[RD_B] pulse width DS_B [RD_B] DS_B [RD_B] recovery time tTCLK is the cycle of the TCLK. ( i ) BMODE="0" MADD[8:0] tSADDS tHADDS tHCSDS tVDADS tDDAAK tIDADS tDSINT CS_B MD[7:0] DS_B /RD_B tSCSDS tWDS RW_B /WR_B tSRWDS tHRWDS tVAKDS tIAKDS ACK_B /RDY_B ( ii )BMODE="1" MADD[8:0] tSADDS CS_B MD[7:0] tVDADS tDDAAK DS_B /RD_B tW DS RW_B /WR_B tSRWDS ACK_B /RDY_B tVAKDS tIAKDS tHRWDS tIDADS tDSINT tSCSDS tHADDS tHCSDS Data Sheet S12953EJ4V0DS00 27 PD98411 b) Internal Register Write Parameter Symbol Conditions MIN. TYP . MAX. Unit Address setting time (vs. DS_B[RD_B]) CS_B setting time (vs. DS_B[WR_B]) R/W_B[RD_B] setting time (vs. DS_B[WR_B]) Data setting time (vs. DS_B[WR_B]) Address hold time (vs. DS_B[WR_B]) CS_B hold time (vs. DS_B[WR_B]) R/W_B[RD_B] hold time (vs. DS_B[WR_B]) Data hold time (vs. DS_B[WR_B]) tSADDS tSCSDS tSRWDS tSDADS tHADDS tHCSDS tHRWDS tHDADS tVAKDS tIAKDS tWDS tDSINT Load capacitance: 30 pF Load capacitance: 30 pF 10 5 5 15 4 0 0 4 15 10 51.44 51.44 ns ns ns ns ns ns ns ns ns ns ns ns S S DS_B[RD_B] ACK_B[RDY_B] output delay DS_B[RD_B] ACK_B[RDY_B] float delay DS_B [RD_B] pulse width DS_B [RD_B] DS_B [RD_B] recovery time tTCLK is the cycle of the TCLK. ( i )BMODE="0" MADD[8:0] tSADDS CS_B tSCSDS MD[7:0] tSDADS DS_B /RD_B tWDS RW_B /WR_B tSRWDS ACK_B /RDY_B tVAKDS tIAKDS tHRWDS tDSINT tHDADS tHADDS tHCSDS ( ii ) BMODE="1" MADD[8:0] tSADDS CS_B MD[7:0] tSDADS RW_B/WR_B DS_B/RD_B tSRWDS ACK_B/RDY_B tVAKDS tIAKDS tHRWDS tWDS tDSINT tHDADS tSCSDS tHADDS tHCSDS 28 Data Sheet S12953EJ4V0DS00 PD98411 OAM Interface Parameter Symbol Conditions Load capacitance: 30 pF MIN. TYP . MAX. 25 25 Unit ns ns S REFCLK PALM3[2:0] -PALM0 tDARRL [2:0] delay REFCLK PHINT3- PHINT 0 tDRFINT delay REFCLK tDARRL PALM3[2:0]PALM0[2:0] REFCLK tDRFINT PHINT3_B-PHINT0_B tDRFINT tDARRL Control Signal Interface Parameter TFSS setting time (vs. TCL) TFSS hold time (vs. TCL) Symbol tSTFTL tHTFTL tDTFTL tDRFRL tSCMRF tHCMRF tSSDRF tHSDRF Load capacitance: 30 pF Load capacitance: 30 pF 20 5 20 5 Conditions MIN. 20 5 25 25 TYP . MAX. Unit ns ns ns ns ns ns ns ns S S TCL TxFP delay RCL RxFP delay CMD setting time (vs. REFCLK) CMD hold time (vs. REFCLK) SD setting time (vs. REFCLK) SD hold time (vs. REFCLK) TCL tDTFTL TFSS tSTFTL TXFP RCL tDRFRL RXFP REFCLK CMD3-CMD0 tSCMRF SD3-SD0 tSSDRF tHSDRF tHCMRF tDRFRL tHTFTL tDTFTL Data Sheet S12953EJ4V0DS00 29 PD98411 UTOPIA Interface (transmission side) Parameter TCLK cycle time TCLK high-level width TCLK low-level width Symbol tCYTK tWTKH tWTKL tDCATK tVCATK tICATK tSDITK tHDITK tSSOTK tHSOTK tSPRTK tHPRTK tSADTK tHADTK tSENTK tHENTK tCYTK tWTKH TCLK tSADTK TADD2[4:0] TADD1[4:0] TCLAV3-TCLAV0 tVCATK TENBL2_B, TENBL1_B TSOC2,TSOC1 tSDITK TDI[7:0] tSPRTK TPR2,TPR1 tHPRTK tHDITK tSSOTK tSENTK tDCATK tDCATK tHADTK tICATK tWTKL Load capacitance: 30 pF Load capacitance: 30 pF Load capacitance: 30 pF Conditions MIN. 20 0.4xtCYTK 0.4xtCYTK 1 1 1 4 1 4 1 4 1 4 1 4 1 TYP . MAX. 125 0.6x tCYTK 0.6x tCYTK 14 14 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns S S S TCLK TCLAV delay TCLK TCLAV output delay TCLK TCLAV data float delay TDI[0]-TDI[7] setting time (vs. TCLK) TDI[0]-TDI[7] hold time (vs. TCLK) TSOC setting time (vs. TCLK) TSOC hold time (vs. TCLK) TPR setting time (vs. TCLK) TPR hold time (vs. TCLK) TADD0- TADD 7 setup time (vs. TCLK) TADD0- TADD7 hold time (vs. TCLK) TENBL_B setting time (vs. TCLK) TENBL_B hold time (vs. TCLK) tHSOTK tHENTK 30 Data Sheet S12953EJ4V0DS00 PD98411 UTOPIA Interface (reception side) Parameter RCLK cycle time RCLK high-level width RCLK low-level width Symbol tCYRK tWRKH tWRKL tDCARK tVCARK tICARK tDDORK tVDORK tIDORK tDSORK tVSORK tISORK tDPRRK tVPRRK tIPRRK tSADRK tHADRK tSENRK tHENRK Load capacitance: 30 pF Load capacitance: 30 pF Load capacitance: 30 pF Load capacitance: 30 pF Load capacitance: 30 pF Load capacitance: 30 pF Load capacitance: 30 pF Load capacitance: 30 pF Load capacitance: 30 pF Load capacitance: 30 pF Load capacitance: 30 pF Load capacitance: 30 pF Conditions MIN. 20 0.4xtCYRK 0.4xtCYRK 1 1 1 1 1 1 1 1 1 1 1 1 4 1 4 1 TYP . MAX. 125 0.6xtCYRK 0.6xtCYRK 14 14 20 14 14 20 14 14 20 14 14 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns S S S S S S S S S S S S RCLK RCLAV delay RCLK RCLAV output delay RCLK RCLAV data float delay RCLK RDO delay RCLKRDO output delay RCLKRDO data float delay RCLK RSOC delay RCLK RSOC output delay RCLK RSOC data float delay RCLK RPR delay RCLK RPR output delay RCLK RPR data float delay RADD setting time (vs. RCLK) RADD hold time (vs. RCLK) RENBLB setting time (vs. RCLK) RENBLB hold time (vs. RCLK) tCYRK tWRKH RCLK RADD2[4:0], RADD1[4:0] RCLAV3-RCLAV0 RENBL2_B, RENBL1_B tSENRK RSOC2,RSOC1 tISORK RDO[15:0] tIDORK RPR2,RPR1 tIPRRK tVPRRK tDPRRK tDPRRK tVDORK tDDORK tDDORK tVSORK tDSORK tDSORK tDCARK tDCARK tICARK tVCARK tWRKL tSADRK tHADRK tHENRK Data Sheet S12953EJ4V0DS00 31 PD98411 PMD Interface (transmission side) Parameter REFCLK cycle time Note Symbol tCYRF tWRFH tWRFL tCYSF Conditions MIN. -20ppm 0.4xtCYRF 0.4xtCYRF -0.005UI TYP . 51.4403 MAX. +20ppm 0.6xtCYRF 0.6xtCYRF Unit ns ns ns ns REFCLK high-level width REFCLK low-level width TFKT(C) cycle time Note 6.43 +0.005UI To get the transmit source clock which is a jitter below 0.01UI, the basis signal which has at least equal or more than 40-ppm precision must be inputted. (i) When using Clock Synthesizer tCYFR tWRFH REFCLK TDOT3-TADT0 (TDOC3-TDOC0) tWRFL (ii) When using external serial clock tCYSF TFKT (TFKC) TDOT3-TDOT0 (TDOC3-TDOC0) PMD Interface (reception side) Parameter RDIT(C) setting time (vs. TFKT(C)) RDIT(C) hold time (vs. TFKT(C)) Symbol tSDISC tHDISC Conditions When using external PLL When using external PLL MIN. 1.0 4.0 TYP . MAX. Unit ns ns TFKT (TFKC) tSDISC RDIT3-RDIT0 (RDIC3-RDIC0) tHDISC 32 Data Sheet S12953EJ4V0DS00 PD98411 3. PACKAGE DRAWING 240-PIN PLASTIC QFP (FINE PITCH) (32x32) A B 180 181 121 120 detail of lead end S C D Q R 240 1 61 60 F G P H I M J K M N S L S ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 34.60.2 32.00.2 32.00.2 34.60.2 1.25 1.25 0.22 +0.05 -0.04 0.10 0.5 (T.P.) 1.30.2 0.50.2 0.17 +0.03 -0.07 0.10 3.20.1 0.40.1 3 +7 -3 3.8 MAX. NOTE Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. P240GN-50-LMU, MMU, SMU-4 Data Sheet S12953EJ4V0DS00 33 PD98411 4. RECOMMENDED SOLDERING CONDITIONS The conditions listed below shall be met when soldering this product. For more details, refer to our document "Semiconductor Device Mounting Technology Manual (C10535E)". Please consult with our sales offices in case other soldering process is used, or in case the soldering is done under different conditions. Surface-mount devices *PD98411GN-MMU: 240-pin plastic QFP (fine pitch) (32 x 32 mm) Soldering process Infrared ray reflow Soldering conditions Peak package's surface temperature :235 C or below, Reflow time : 30 seconds or below (210 C or higher), Number of reflow profess : 1, Exposure limit :3 days (36 hours pre-backing is required at 125C afterwards) Terminal temperature :300 C or below, Flow time : 3 seconds or below (Per one side of the device). Note Symbol IR35-363-1 Partial heating method -- Note Exposure limit before soldering after dry-pack package is opened. Storage conditions: 25 C and relative humidity at 65% or less. 34 Data Sheet S12953EJ4V0DS00 PD98411 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet S12953EJ4V0DS00 35 PD98411 NEASCOT-P40 is a trademark of NEC corporation. The export of this product from Japan is prohibited without governmental license. To export or re-export this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. * The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. * NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. * Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. * While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. * NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. M7 98. 8 |
Price & Availability of UPD98411
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |